The result of the design analysis by ALINT-PRO is a database of rule violations, where the user can query the detailed information about the identified issues, their origin in the RTL code, the descriptions of the issues, and documentation on the violated rules. On the contrary, any of the linting workflow phases can be run in any order assuming that the corresponding dependent design entry phase has already succeeded. The design entry workflow is linear: each subsequent phase can only be executed after the preceding phase succeeds. All these phases verify that the design implementation conforms to the configured rule policy.
The linting workflow splits into "parse linting", "elaboration linting", "synthesis linting", "constraints linting", and "chip linting" phases. The design entry workflow divides into "parse", "elaborate", "synthesize", and "constrain" phases. Running the HDL designs in ALINT-PRO comprises of two key workflows: design entry and linting. The rules cover typical coding mistakes, inconsistent coding style and limited code re-use, sub-optimal synthesis, synthesis vs simulation mismatches, non-portable coding practices, improper clock and reset networks, unsynchronized clock domain crossings, and many more topics.
The primary purpose of applying ALINT-PRO is the Design Rule Checking (DRC) for the RTL code written in VHDL, Verilog and SystemVerilog design subset before running the logic synthesis phase.
Synplify pro export tcl verification#
Use of ALINT-PRO for functional verification on the early project stages makes the RTL design closure highly efficient.
Synplify pro export tcl how to#
This application note gives a basic introduction on how to start working with ALINT-PRO, it familiarizes you with the major features of the product and helps to bring the GUI into use. Global Preferences and Project/File Properties
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